Since germanium (Ge) intrinsically has the highest hole mobility of all group IV and III-V semiconductors and has 2 times higher electron mobility than silicon (Si), Ge is considered to replace Si as p-channel material for future complimentary metal-oxide-semiconductor field-effect transistor (CMOS) nodes. It is foreseen that the high-mobility channel material will be co-integrated with Si-based periphery, such as input/output (I/O), electrostatic discharge (ESD). Hence it is imperative to integrate Ge channels on bulk Si wafers.
Due to the large lattice mismatch of Ge and Si it is challenging to grow low-defective Ge epitaxy on Si. Especially, various defects may be introduced during the epitaxy growth. For example, threading dislocation defects are formed in the epitaxy grown Ge layer. Various methods are used to reduce the hetero-epitaxy related defects such as the threading dislocation defects, stacking faults, point defects etc. However, existing methods have various concerns and disadvantages associated with device quality and reliability. For example, in the existing method, the threading dislocation defect is restrained but not eliminated. Since these defects could be electrically active, the formed transistors might still suffer from an increased junction leakage.
Therefore, there is a need for a structure and method to address these concerns for enhanced performance and reduced junction leakage.